The present invention generally relates to computer systems, and more particularly to an direct memory access (DMA) controllers.
As is well known, DMA transfers involve the movement or transfer of data from one memory device to another memory device (within a computing system) across a system bus, and without intervening communication through a processor. More particularly, a processor such as a CPU typically controls and coordinates the execution of instructions within computing system. Ancillary to this operation, the CPU must frequently move data from a memory or other peripheral device into the CPU for processing, or out of the CPU to a memory or other peripheral device after processing. The CPU also often coordinates the movement of data from one memory or peripheral device to another memory or peripheral device.
In very early computing systems, this latter movement of data was accomplished by first reading the data directly from one memory device into the processor, then immediately writing that same data out to another memory device. As computing systems advanced, DMA controllers were created to facilitate such data transfers by controlling the movement of data directly from one memory device to another memory device. FIG. 1 shows a block diagram illustrating certain fundamental components of a computer system that are utilized in connection with such a conventional DMA transfer. In this regard, a single DMA controller 10 is illustrated in connection with a source memory 12, a destination memory 14 and a CPU or some other processing circuit 16. Each of the devices is illustrated as being interconnected, or otherwise disposed for intercommunication, via a bus 18, which preferably comprises both address and data lines. The devices are also interconnected through various control and other signaling lines 19, 20, 21, and 22. In operation, data 24 may be directly transferred between memory devices 12 and 14 across the bus 18, without having to transition through the CPU 16, which allows data to be transferred between the memories at a much higher rate.
As is known, there are three primary steps involved in a DMA transfer. First, the processor 16 sets up the DMA transfer by supplying a DMA controller 10 with the identity of the source and destination memories 12 and 14, the address of the first bit to byte to be transferred from the source memory 12, as well as the number of bytes to be transferred. Once the CPU 16 has communicated this information to the DMA controller 10, the DMA controller 10 starts the operation by either taking control of the bus 18, or otherwise requesting shared control of the bus with other devices (not shown). In this regard, other devices that are disposed along the same bus 18 may share the bus, the allocation of which may be controlled by an arbitration circuit (not shown), as is understood by those skilled in the art. Once the DMA controller 10 has the bus 18, it initiates the bus transfer (assuming that the data is available for transfer). In this regard, and as will be understood by persons skilled in the art, if the data were temporarily stored within a cache memory, or some other device (not shown), then the data actually stored in the memory device 12, would be considered xe2x80x9cdirty dataxe2x80x9d, and therefore not subject to transfer. Resolution of nuances such as this are known by those skilled in the art, and need not be discussed herein, in order to effectively illustrate the basic DMA operations as are known by prior art systems.
Utilizing control lines 21 and 22, the DMA controller 10 may orchestrate the transfer of data from the source memory 12 to the destination memory 14. The DMA controller 10 may control the address supplied on address bus 18, as well as the chip select and enable lines necessary in order to read data from a select memory address of the source memory 12 and write that same data to a select memory address in the destination memory 14. Assuming that a plurality of data bytes are to be transferred from the source memory 12 to the destination memory 14, then the DMA control 10 will update the addresses on bus 18 accordingly. Once the DMA transfer is complete, the DMA controller 10 may interrupt the CPU 16 to inform it accordingly. It will be appreciated that throughout the duration of the DMA transfer, the CPU 16 may be performing various processing operations. As is known, this greatly enhances the overall efficiency of the system by allowing the CPU 16 to perform processing tasks, without having to get bogged down in managing simple data transfers between memory devices.
In more complex systems of the prior art, however, more than one DMA controller device may be needed. To illustrate, reference is made to FIG. 2, which is a block diagram illustrating a system similar to the system of FIG. 1, but illustrating additional DMA controllers 30, 32, and 34, along with multiple memory devices 42, 44, 46, and 48. For simplicity, the various control and signaling lines have not been illustrated in FIG. 2. For purposes of illustrating this aspect of the prior art, an arbitration circuit 40 is shown. As is known, when multiple DMA controllers 30, 32, and 34 are provided in a system, then some sort of arbitration circuit 40 is provided to ensure that bus conflicts do not occur.
While the prior art architecture illustrated in FIG. 2 effectively works to allow the operation of multiple DMA controllers 30, 32, and 34 in a system, it nevertheless suffers from the shortcoming of requiring additional arbitration circuitry 40.
There is therefore a need for a system that provides effective DMA management from multiple controllers, while eliminating separate and independent arbitration circuitry.
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the foregoing and other objects, the present invention is directed to an improved direct memory access controller, having built-in arbitration circuitry, whereby multiple, identical, DMA controllers may be cascaded within a computing system, without requiring additional (i.e., separate) arbitration circuitry. In accordance with one aspect of this invention, a DMA controller is provided having a first input for connection to a DMA Acknowledge signal, and a first output for connection to a DMA Request. A second output is also provided for carrying a signal that is representative of activity of the DMA controller. In this regard, the second output may be configured to output a signal in either an Enable state or Inhibit state. If the DMA controller is active (i.e., presently controlling the transfer update among memory devices), then the second output is placed in an Inhibit state. Otherwise, the second output is controlled to be in an Enabled state. In this way, this second output is configured for direct connection to a first input of a second, similar, DMA controller device. Further, the DMA controller includes a sense circuit that is configured to detect a state of the DMA Request signal. Finally, the DMA controller includes a controller circuit that is responsive to both the first input and the sense circuit, and is configured to generate the second output.
It should be appreciated that, when multiple DMA controllers of this type are utilized together, their first output signals may be directly connected to each other, and to the Request signal that is communicated to a processor. This is the signal that requests permission for a given device to initiate or otherwise begin a DMA transfer. Only the first DMA controller, however, has an input that is directly connected to the Acknowledge signal that is provided by the processor. Instead, additional DMA controllers that are utilized directly connect their first input to the second output of a preceding, similar DMA controller. The cooperative operation of the sense circuit and the controller circuit, which generates the second output, ensures that when two or more of the DMA controllers simultaneously Request to perform a transfer, only one will actually seize the bus, and therefore bus contention is avoided, without the addition of a separate and independent arbitration circuit.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention, as is defined in the claims. dr
The accompanying drawings incorporated in and forming a part of the specification illustrate several aspects of the present invention, and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a block diagram of a DMA controller in communication with memory and a CPU via a bus;
FIG. 2 is a block diagram of multiple DMA controllers in communication with memory, mass storage and a CPU through an arbitration circuit on a common bus;
FIG. 3 is a block diagram of the present invention with multiple DMA controllers in communication with memory, mass storage and a CPU across a common bus without the use of a separate arbitration circuit;
FIG. 4 is a block diagram showing the principal components of a DMA controller constructed in accordance with the present invention; and
FIG. 5 is a block diagram showing multiple DMA controllers of the present invention, which include state machines, in communication across a common bus.